A Power Distribution Network (hereinafter “PDN”) delivers power and ground voltages from pad locations to all devices in an integrated circuit (hereinafter “IC”). In general, after a layout of the IC (and the PDN) is designed, various subsequent testing steps are typically performed to verify the layout design work. Conventional testing tools simulate the layout design by assuming that the PDN provides a constant voltage source to each circuit component (e.g., a transistor, etc.) of the IC. This approach is deficient because it does not account for various voltage drops that may occur across the PDN, which are typically referred to as power supply noise of the PDN.
During real operations of the IC, each of the circuit elements of the IC is associated with a voltage drop. Such a voltage drop may be due to various parasitic components (e.g., parasitic resistors, parasitic capacitors, parasitic inductors, etc.) across the PDN. In a non-limiting example, a parasitic resistor may be induced by a resistance of an interconnect wire that connects a power supply pad to a circuit component (e.g., a transistor) and a corresponding voltage drop may be equal to the resistance times a current flowing through the resistor. Moreover, due to rapid advances in semiconductor technology, today's IC can include millions of circuit components. A cumulative effect of respective voltage drops may lead to performance degradation or even critical failures of the IC. This is especially the case in low-power and high-performance IC's. If a supply voltage at a circuit component is decreased due to the voltage drop, the circuit component may not switch at a desired time, which may in turn cause malfunction of the circuit component and a corresponding larger circuit as a whole. Thus, there exists a need for method and system that can effectively, efficiently, and quickly perform a voltage drop analysis of the PDN for an IC design.